This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 11-187029, filed Jun. 30, 1999, the entire contents of which are incorporated herein by reference.
The present invention relates to a pattern exposure apparatus and method for use in transferring a circuit pattern of a mask to a semiconductor wafer in manufacturing a semiconductor device, and more particularly, an apparatus and method for controlling the surface of the semiconductor wafer on which light is applied, by tilting the semiconductor wafer.
When a semiconductor element is formed on a semiconductor wafer by a conventional method, a so-called light-exposure step is usually employed. In the light exposure step, a circuit pattern drawn on a reticle is projected onto the wafer by a light exposure apparatus called a stepper and thereby reduced and transferred onto the wafer.
In the light exposure step, the circuit pattern of a single chip or a plurality of chips are transferred to a predetermined portion of the pattern formation region of a semiconductor wafer in a first light exposure step. Subsequently, a second light-exposure step is performed, in which another circuit pattern of a single chip or a plurality of chips are transferred to an adjacent part by moving the light exposure apparatus. If the light exposure process mentioned above is repeated a plurality of times while moving the light-exposure position, the entire circuit pattern is transferred to the pattern formation region of the semiconductor wafer.
In this light exposure step, if the surface of the semiconductor wafer is not flat but significantly uneven, the distance between a lens of the pattern exposure apparatus and a light-receiving surface of the wafer varies from part to part. If the variance in distance exceeds a certain limitation, a so-called out-of-focus image is formed. As a result, a transfer pattern becomes blurred. The range of the distance within which no blurred image is formed, is called xe2x80x9cthe depth of focusxe2x80x9d D. There is the following relationship between the depth of focus D, resolution R, an aperture ratio (N/A) of the lens of the stepper, and wavelength xcex of a light source:
R=K1xc3x97xcex/(NA)xe2x80x83xe2x80x83(1)
D=K2xc3x97xcex/(NA)xe2x80x83xe2x80x83(2)
where K1, K2 are constants.
The resolution R in the aforementioned equation (1) corresponds to a minimum drawing width. The resolution R has been reduced as the semiconductor devices are integrated. To reduce the resolution R, the wavelength of the light source must be reduced. As a result, the depth of focus D is reduced. Since the depth of focus D is reduced, the surface of the wafer is required to be formed much flatter.
Therefore, a mechanism is devised to cope with the case where the degree of flatness of the wafer surface is low. The mechanism is a leveling function and used by setting it in the stepper. More specifically, leveling is made by setting a light-exposure reference plane on the wafer so as to minimize the variation in distance between the lens of the light exposure apparatus and sites of the light-receiving surface of the wafer (said variation is ascribed to the unevenness of the surface) in the region to be exposed to light at one time, and tilting the wafer such that the light-exposure reference plane matches with a light focus plane.
Recently, semiconductor devices have been integrated more and more. The integration of the semiconductor devices is attained by not only reducing the minimum drawing width but also increasing a chip size. This fact means that smaller images requiring low resolutions have to be drawn onto a larger area. To attain this, it is necessary to use a lens having a larger aperture and a smaller aberration. As a result, a higher cost is required not only to design the stepper lens system but also to fabricate the stepper employing such a lens system.
There is another system called xe2x80x9cscan light exposure systemxe2x80x9d. In this system, the entire pattern drawn on the reticle is not transferred to the wafer at one time. Instead, a part of the pattern on the reticle is scanned from one end to the other end and transferred while the wafer is moved. The scan light exposure system has the following advantages. First, a large-size lens is not set in the stepper. Since the area to be exposed at one time (called xe2x80x9cunit exposure areaxe2x80x9d) can be reduced, even if the wafer has an uneven surface, the uneven surface will not have a large effect upon transferring of the pattern. This means that the transferring pattern according to this system is the same as when the pattern is transferred to a substantially flat wafer surface.
When a wafer is manufactured, the surface of the wafer is usually polished with a polishing agent such as a colloidal silica to form a mirror surface. More specifically, the wafer surface is placed on a polishing cloth (urethane or non-woven cloth), and is swung and rotated while the wafer surface is pressurized. In this step, since weight is applied onto the wafer, the wafer is more or less sunk into the polishing cloth. The peripheral portion of a wafer edge is brought into contact with the polishing cloth at an angle. As a result, the edge of the peripheral portion of the wafer is selectively polished and rounded off. Therefore, the xe2x80x9crounded off portionxe2x80x9d is inevitably formed in the peripheral portion of the wafer edge.
Since the xe2x80x9crounded off portionxe2x80x9d is present, the flatness of the surface is significantly reduced on the peripheral portion. Therefore, it becomes very difficult to level the wafer surface of the peripheral portion in order to reduce the degree of the roughness of the surface, during the light exposure step. To explain in other words, leveling (tilting the wafer) is not performed regularly, with the result that a leveling error occurs more frequently.
There is another advantage of the scan light-exposure stepper. If a chip size is smaller than the area exposed to light from the stepper at one time, a plurality of chips can be simultaneously exposed to the light. Therefore, the time required for applying light to the entire surface of a wafer can be reduced. Since a light-exposure unit area is small, the light-exposure reference plane is more easily performed in accordance with the degree of roughness of the wafer surface.
Problems occur when a circuit pattern is transferred to the region including a peripheral portion of the wafer edge. We will now explain the problems with reference to FIG. 1A to FIG. 1E.
FIG. 1A is a plan view of a semiconductor wafer. The region surrounded by vertical lines 51 and horizontal lines 52 on the figure is an area which can be exposed to light at one time in a single scanning operation (called xe2x80x9cunit scan regionxe2x80x9d). FIG. 1B and FIG. 1C show enlarged plan views of the unit scan region. FIG. 1D is a cross-sectional view taken along the line 1Dxe2x80x941D of FIG. 1B. FIG. 1E is a cross sectional view taken along the line 1Exe2x80x941E of FIG. 1C.
As shown in FIG. 1A, an edge exclusion line 54 is usually drawn inside an outer circumference 53 on the semiconductor wafer. The edge exclusion line 54 is used to divide between an effective element region (inside the line) and the xe2x80x9crounded offxe2x80x9d peripheral edge portion (outside the line). Now, a case is assumed that a pattern drawn on a reticle is transferred onto the unit scan region (indicated by an open-circle ∘ in FIG. 1A) including the rounded off peripheral region by scanning a unit light exposure region 55, as shown in FIGS. 1B and 1C.
When light is applied to an effective chip region alone (as shown in FIG. 1B), the light-exposure reference plane is obtained relatively flat as shown in FIG. 1D. Whereas, when light is applied to a region including an ineffective chip region (as shown in FIG. 1C), the light-exposure reference plane is inclined as shown in FIG. 1E. This is because the light-exposure reference plane is set so as to off set the xe2x80x9crounded offxe2x80x9d surface of the peripheral portion. The term xe2x80x9ceffective chip regionxe2x80x9d used herein is an area for forming one chip, which is set within the effective element region, in which the ineffective element region (rounded off surface) is not included. The term xe2x80x9cineffective chip regionxe2x80x9d is a region for forming one chip, in which the ineffective element region (rounded off region) is included.
Since the ineffective chip region including the peripheral region and the effective chip region are present in the same light exposure unit area, the effective chip region is influenced by the xe2x80x9crounded offxe2x80x9d peripheral portion. If the xe2x80x9crounded offxe2x80x9d portion is large, a part of the effective chip region falls outside the depth of focus. As the result, the transferred pattern is blurred, providing defective elements. Accordingly, the number of chips having a good light exposure pattern (indicated by an open circle ∘ in FIG. 1C) decreases. In the figure, reference symbol X indicates a chip having a defective light exposure pattern.
As described in the above, the conventional scan light exposure method to a semiconductor wafer has the following problems. Since the effective chip region belongs to the same light exposure unit as the ineffective chip region including a peripheral portion, the effective chip region is influenced by the rounded off surface. If the degree of the rounding off is large, a part of the effective chip region falls outside the depth of focus. The resultant pattern is blurred, producing defective elements.
The present invention was made to solve the aforementioned problems. An object of the present invention is to provide a pattern exposure apparatus and method for a semiconductor wafer capable of reducing occurrence of a blurred pattern which is produced by the influence of an inevitably-formed rounded off portion of the peripheral edge portion of the wafer, during a circuit pattern is transferred to the semiconductor wafer.
To attain the aforementioned object, according to one aspect of the present invention, there is provided a pattern exposure apparatus for a semiconductor wafer comprising:
a light-exposure section for applying light to a predetermined region on a semiconductor wafer,
the predetermined region including at least either one of or a part of both an effective element region and an ineffective element region, and
the semiconductor wafer having the effective element region in which an element is formed and the ineffective element region in which no element is formed;
an unevenness measuring section for measuring unevenness of a surface of the semiconductor wafer at a plurality of sites within the predetermined region and outputting unevenness data;
a calculating section for obtaining a reference plane through calculation using unevenness data of the effective element region alone, after unevenness data of the ineffective element region is eliminated from the unevenness data output from the unevenness measuring section, the reference plane being used as a reference when light is applied to the predetermined region; and
an inclination control mechanism for controlling inclination of the semiconductor wafer in accordance with the reference plane obtained through the calculation performed by the calculating section.
In the pattern exposure apparatus thus constructed, an evaluation process for determining the reference plane is performed in the predetermined region to be exposed at one time, by using the unevenness data of the effective element region alone without using unevenness data of the ineffective element region of the surface of the semiconductor wafer. In this manner, it is possible to reduce occurrence of a blurred pattern (which is formed due to the presence of the rounded-off peripheral portion of the semiconductor wafer) even if the semiconductor wafer does not have a flat surface, in particular, a rounded off peripheral portion is present in the edge portion of the semiconductor wafer.
According to a second aspect of the present invention, there is provided a pattern-exposure apparatus for a semiconductor wafer comprising:
a light-exposure section for applying light to a predetermined region on a semiconductor wafer,
the predetermined region including at least either one of or a part of both an effective chip region and an ineffective chip region,
the semiconductor wafer having the effective chip region and the ineffective chip region,
the effective chip region being set within an effective element region in which an element is formed, and required for forming a single chip therein, and
the ineffective chip region including an ineffective element region in which no element is formed and required for forming a single chip therein;
an unevenness measuring section for measuring unevenness of a surface of the semiconductor wafer at a plurality of sites within the predetermined region and outputting unevenness data;
a calculating section for obtaining a reference plane through calculation using unevenness data of the effective chip region alone, after unevenness data of the ineffective chip region is eliminated from the unevenness data output from the unevenness measuring section, said reference plane being used as a reference when light is applied to the predetermined region; and
an inclination control mechanism for controlling inclination of the semiconductor wafer in accordance with the reference plane obtained through the calculation performed by the calculating section.
In the pattern exposure apparatus thus constructed, an evaluation process for determining the reference plane is performed in the predetermined region to be exposed at one time, by using the unevenness data of the effective element region alone without using unevenness data of the ineffective element region of the surface of the semiconductor wafer. In this manner, it is possible to reduce occurrence of a blurred pattern (which is formed due to the presence of the rounded-off peripheral portion of the semiconductor wafer) even if the semiconductor wafer does not have a flat surface, in particular, a rounded off peripheral portion is present in the edge portion of the semiconductor wafer.
According to a third aspect of the present invention, there is provided a pattern exposure method for a semiconductor wafer, comprising the steps of:
measuring degree of unevenness of a surface of the semiconductor wafer at a plurality of sites within a predetermined region on the semiconductor wafer and outputting unevenness data;
obtaining a reference plane for use in applying light to the predetermined region, through calculation using only unevenness data of an effective chip region of the unevenness data output, the effective chip region being within an effective element region in which an element is formed and required for forming a single chip; and
controlling inclination of the semiconductor wafer in accordance with the reference plane obtained.
In the pattern exposure method thus constituted, an evaluation process for determining the reference plane is performed in the predetermined region to be exposed at one time, by using the unevenness data of the effective element region alone without using unevenness data of the ineffective element region of the surface of the semiconductor wafer. In this manner, it is possible to reduce occurrence of a blurred pattern (which is formed due to the presence of the rounded-off peripheral portion of the semiconductor wafer) even if the semiconductor wafer does not have a flat surface, in particular, a rounded off peripheral portion is present in the edge portion of the semiconductor wafer.
According to a fourth aspect of the present invention, there is provided a pattern exposure method for a semiconductor wafer comprising the steps of:
determining whether or not at least a part of an ineffective chip region is included in a predetermined region on the semiconductor wafer; the ineffective chip region including an ineffective element region in which no element is formed and required for forming a single chip;
measuring unevenness of a surface of the semiconductor wafer at a plurality of sites of the predetermined region excluding the ineffective chip region and outputting unevenness data;
obtaining a reference plane for use in applying light to the predetermined region, through calculation using the unevenness data output; and
controlling inclination of the semiconductor wafer in accordance with the reference plane obtained.
In the pattern exposure method thus constituted, an evaluation process for determining the reference plane is performed in the predetermined region to be exposed at one time, by using the unevenness data of the effective element region alone without using unevenness data of the ineffective element region of the surface of the semiconductor wafer. In this manner, it is possible to reduce occurrence of a blurred pattern (which is formed due to the presence of the rounded-off peripheral portion of the semiconductor wafer) even if the semiconductor wafer does not have a flat surface, in particular, a rounded off peripheral portion is present in the edge portion of the semiconductor wafer.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.